The present invention relates to a semiconductor device manufacturing method and a semiconductor wafer. More particularly, the invention relates to an improved method of manufacturing, over the principal plane of a semiconductor wafer, semiconductor devices each having a plurality of bump electrodes therein.
Japanese Unexamined Patent Application Publication No. 2007-36129 describes a technology in which a passivation film is removed from the scribe lines in such a manner that the film is left intact over regions several millimeters from the wafer periphery, so that the gap between the scribe lines and a protective tape is closed before the wafer periphery is reached.
Japanese Unexamined Patent Application Publication No. Hei 11(1999)-45868 describes a technology in which components having the same pattern as that of the components in a product chip area are formed in a pseudo chip area where incomplete pseudo chips failing to make up product chips are formed, so as to improve the uniformity of the thickness of a polishing film left from the chemical mechanical polishing (CMP) process.